1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device having a multi-layered wiring structure.
2. Description of the Related Art
FIG. 3 is a plan view showing a structure around a bonding pad of a semiconductor device to which the present invention is not applied.
This semiconductor device comprises bonding pad 31 applied with a ground potential, first line 32 led from bonding pad 31 and connected to a ground terminal of first analog circuit 33, second line 34 led from bonding pad 31 and connected to a ground terminal of second analog circuit 35, and third line 36 led from bonding pad 31 and connected to a ground terminal of third analog circuit 37.
In such a semiconductor device, since lines 32, 34 and 36 are branched from bonding pad 31 and respectively connected to the analog circuits 33, 35 and 37, an impedance of a common line portion of lines 32, 34 and 36 can be suppressed, thereby reducing interference among circuits No. 1 to No. 3.
In the above semiconductor device, in order to reduce the interference among the circuits so as to suppress the impedance of a common line portion of lines 32, 34 and 36, lines 32, 34 and 36 are branched from bonding pad 31 to analog circuits 33, 35 and 37. In this case, since the area of the semiconductor substrate is limited, when three lines 32, 34 and 36 are used for connecting analog circuits 33, 35 and 37 to bonding pad 31, the width of each line must be decreased. As a result, the impedance (direct-current resistance) of each line is increased.